Gobi, Mojave, and the Future of the G3

The PowerPC 750 processor, more popularly referred to as the G3, has been around for nearly six years now, and most of the PPC chip excitement today is focused on the IBM PPC 970, dubbed the G5 by Apple's marketeers. However, the old G3 750 has new life in it yet, and I'm provisionally expecting the next generation of Apple iBooks to remain G3 powered.

Back in 1997 when the PPC 750 was introduced, it had two important innovations. First, "these chips were optimized to run real software, not some theoretical ideal. Early benchmarks show the 750 outperforming the 604e...."

Second, the PPC 750 supported a dedicated "backside" bus for communicating with a closely coupled level 2 (L2) cache, connected to the core by a 64-bit bus. (On earlier PPC Macs, the L2 cache ran at system bus speed, which topped out at 50 MHz) Apart from reducing system bus congestion, the use of a separate L2 cache bus allowed the CPU core to retrieve its data from the cache much faster than earlier generations of processors, and hence cut computation time down significantly.

The G3 thus facilitated a quantum leap in PowerPC performance, eclipsing overnight the previous 601, 603, and 604 variants of the PPC. For example, the 250 MHz PPC 750 G3 used in the original G3 PowerBook (3500) offered roughly twice the power of the 240 MHz PPC 603e used in it's immediate predecessor, the top-of-the-line PowerBook 3400.

IBM's later editions of the 750, known as 750CX/e/FX (which have been used in iBooks since the September 2000 "Paris" models) incorporate a wider (256 bit) L2 cache bus and incorporate the L2 cache on the chip itself. This means the L2 cache runs at full CPU speed, eliminating the slower external backside cache used in earlier G3 model.

The 750FX used in the current 800 MHz and 900 MHz iBooks is architecturally based on the PowerPC 750 and PowerPC 750CXe processors and incorporates 512 KB of internal L2 cache running at core frequency with cache locking, expanded width of internal data paths, additional cache buffers, parity protection on internal cache arrays, and additional memory mapping registers.

The internal L2 cache operates at the processor's core frequency, providing reduced latency and increased performance compared with the original PPC 750's external half-speed L2. The larger size of the internal L2, twice that on the 750CXe, provides more on-chip memory storage for application code and data and can give an estimated 8 to 15 percent performance improvement due to the size alone.

The 750FX is produced on a .13 micron process with Low-K Dielectric and Silicon-on-Insulator technology. The 512 KB L2 cache substantially enhances performance in contrast to the 256 KB cache in the earlier 750CXe. There are also 256-bit cache lines instead of 64-bit, in addition to improved logic. The larger cache and wider bus can improve performance by 25% over the 750CXe at the same clock speed.

The IBM 750FX was originally intended to reach 1 GHz, but reportedly technical obstacles to going beyond 900 MHz have been encountered, and in June IBM announced the next G3 750 family chip, the 750GX, code named "Gobi" continuing IBM's desert theme. The 750FX chips are code named "Sahara."

IBM engineer Mark Schaffer described the 750GX as "offering world-class performance at very low power levels utilizing its leading-edge process technologies to meet these requirements."

Production of the 750GX is targeted for December 2003, and it would seem like a logical candidate to power the next iBook upgrade, but Apple has not tipped its hand. There is continued speculation about the iBook going G4, but the G3 has formidable advantages in terms of low power consumption and relatively low heat generation that make it a more ideal CPU for portable computers than the G4, at least for users who aren't heavily into running AltiVec optimized software such as Adobe Photoshop. With non-optimized applications (i.e., most applications), there will be little difference in performance whether you're using a G3 or a G4.

Manufactured using the same 0.13-micron copper process with Silicon-on-Insulator technology that are used in the current 750FX "Sahara" G3s (on which it is based), the 750GX will be offered at frequencies up to 1.1 GHz. A 1.1 GHz 750GX will draw 8 Watts, just over half the 15 Watt power demand of a 1 GHz G4 chip.

The 750GX is architecturally based on the PowerPC 750FX processor, and includes 1 MB of L2 cache, 4-way set-associative, running at core frequency with cache locking by way, additional L1 and L2 cache buffers allowing pipelining of up to four data cache miss operations, and the capability for up to 200 MHz operation of the 60x system bus interface with additional bus pipelining.

According to Mark Schaffer, an Advanced Technology Engineer with IBM:

"The integrated 1 MB of L2 cache operates at the processor's core frequency, providing minimal latency for instruction fetch operations and data load operations that hit in the L2 cache. The larger size of the internal L2, twice that available on the 750FX, provides more on-chip memory storage for performance-critical application code and data, and may provide a significant performance improvement, due to the size alone. In addition, the L1 data cache path to the Bus Interface Unit (BIU) and the L2 cache reload path to the L1 data cache are 256 bits wide. With these wide data paths, cache line data bursts can be read from or written to the cache array in a single cycle, reducing cache contention between the BIU and the load-store unit. With 1 MB of low-latency integrated L2 cache, the 750GX is designed to reduce the overall system cost and power by eliminating the need for external L3 memory arrays and lowering the board space requirements....

"Cache line miss buffers have been added between the L1 data cache and the L2 cache as well as between the L2 cache and the BIU, allowing for up to four-deep pipelining of L1 cache miss transactions. The four transactions can be either four data cache miss transactions or a combination of three data cache miss transactions and one instruction cache miss transaction. In addition, the BIU in the 750GX has been enhanced to provide support for the deeper cache miss pipelining and can now pipeline up to five load/store bus transactions, four from the L2 cache miss queues and one from the L2 cache cast-out buffer. With this enhanced pipelining from the L1 cache through the L2 cache and out to the bus interface unit, the 750GX is designed to improve the overall system performance and bus utilization, allowing applications to take advantage of the higher processing capability that the 750GX processor offers.

"The L2 cache has also been enhanced to provide an instruction-side-only mode, which allows only the L1 instruction cache transactions to be allocated within the L2 cache. Data-side transactions are not allocated in the L2 and are read from and written to memory directly from the L1 data cache. This mode is useful for applications that do not benefit from the data-side cache and improves the performance of the L2 cache for the instruction side by not replacing L2 cache lines due to data load and store operations."

Schaffer also says that the 750GX is fully user-code-compatible with the other members of the IBM 7xx processor family, providing an easy software-migration path to higher processing performance, which would make it an easy speed bump for 750FX machines like the iBook - and also a candidate for processor upgrade products like PowerLogix's PowerBook Pismo G3 upgrades, currently offered at 800 MHz and 900 MHz with 750FX chips. The 750GX is pin- and voltage-compatible with the 750FX, allowing for use of a common board design. However, the 750GX is physically larger than the 750FX: 51.9 mm square compared to 36.6 mm square, and draws more power (8.0 W at 1 GHz vs. 5.4 W with the 750FX at 800 MHz.

The IBM 32 bit PowerPC 7xx processor family

• 750CXe: 400-600 MHz, 256 KB L2 cache, 6.0 W @ 600 MHz
• 750FX: 600-900 MHz, 512 KB L2 cache, 5.4 W @ 800 MHz
• 750GX: 733 MHz to 1.1 GHz, 1 MB L2 cache, 8.0 W @ 1 GHz

iBook G3 clock speeds and G3 chip versions:

• iBook, 300 MHz 750
• iBook SE, 366 MHz 750
• iBook 366, 366 MHz 750CX
• iBook SE 466, 466 MHz 750CX
• iBook 500, 500 MHz 750CXe
• iBook 600, 600 MHz 750CXe
• iBook 600 14", 600 MHz 750CXe
• iBook 600 (second edition), 600 MHz 750FX
• iBook 700, 700 MHz 750FX
• iBook 700 14", 700 MHz 750FX
• iBook 700 (second edition), 700 MHz 750FX
• iBook 800, 800 MHz 750FX
• iBook 800 14", 800 MHz 750FX
• iBook 800 (second edition), 800 MHz 750FX
• iBook 900, 900 MHz 750FX
• iBook 900 14", 900 MHz 750FX

An even faster IBM 750VX series chip of 1.4 - 1.6 GHz is reportedly in the works, code named "Mojave," and rumored to incorporate a vector processing engine (G4 AltiVec-style). Since one of the most substantial differences between a G3 and a G4 is the vector engine, it is possible that iBooks (or even PowerBooks?) with the Mojave chip inside could be marketed as G4s, although that's just speculation at this point.