The “power user” second generation PowerPC (PPC) CPU was the 604, unveiled in December 1994 along with the 603. Containing 3.6 million transistors, drawing twice the power of the 601, and with a dual L1 cache (16 KB for instructions, 16 KB for data), this workhorse could deal with four instructions per cycle. The 604 started at 100 MHz and went as high as 180 MHz, running at 2x to 4x bus speed. It was first used in the Power Mac 7600, 8500, and 9500.
With its larger L1 cache, the 604 didn’t suffer the same kind of performance issues as the PPC 603 did when running 680×0 software in emulation.
The 604 was designed to work in tandem with other 604s, making it possible to design computers with two or more CPUs. Daystar was the first to do this. Seeing Daystar’s success, Apple licensed the multiprocessor technology and incorporated it into the Mac OS. Maximum bus speed supported by the CPU is 50 MHz.
The 604 has six independent executions units: two single-cycle integer units, a multi-cycle integer unit, a floating point unit, a branch prediction unit, and a load/store unit. This made it an incredible number cruncher and a top choice for Photoshop users.
The 604 was later tweaked for even more performance, giving us the 604e in July 1996. As with the 603e, the newer CPU doubled the size of the instruction and data caches, significantly improving performance. On top of that, the 604e can process up to six instructions per cycle, 50% more than the 604, so overall performance was about 25% higher than the 604 at the same clock speed. Transistor count reached 5.1 million.
While the 604 topped out at 180 MHz, the 604e began at 166 MHz and went as high as 233 MHz on a system bus as fast as 66 MHz.
PowerPC 604ev ‘Mach 5’
The last revision, known as the 604ev (Mach 5), was introduced in August 1997 and available at speeds from 350 MHz to 400 MHz (Apple only used up to 350 MHz), and it was an energy hog and big heat producer at higher speeds. Bus speeds up to 100 MHz were supported, and the 604e runs at 3x to 7x system bus speed.
PowerPC Family Overview
CPU speed* instructions L1 cache L2 cache 601 60-120 MHz 3 per cycle 32 KB external to 1 MB 603 75-160 MHz 2 per cycle 2x8 KB 603e 100-300 MHz 2 per cycle 2x16 KB 604 100-180 MHz 4 per cycle 2x16 KB external to 1 MB 604e 166-233 MHz 6 per cycle 2x32 KB external to 1 MB 604ev 250-350 MHz 6 per cycle 2x32 KB external to 1 MB G3/750 200-450 MHz 3 per cycle 2x32 KB external to 1 MB 750CX 366-466 MHz 3 per cycle 2x32 KB 256 MB onboard 750CXe 400-700 MHz 3 per cycle 2x32 KB 256 MB onboard 750FX 600-900 MHz 3 per cycle 2x32 KB 512 MB onboard 750GX 733-1100 MHz 3 per cycle 2x32 KB 1024 MB onboard G4/7400 350-600 MHz 19 per cycle+ 2x32 KB supports 2 MB L2 cache 7410 466-533 MHz 20 per cycle+ 2x32 KB supports 1 MB L2 cache 7450 667-733 MHz 20 per cycle+ 2x32 KB 256 KB onboard, up to 2 MB L3 7455 600-1420 MHz 20 per cycle+ 2x32 KB 256 KB onboard, up to 2 MB L3 7447A 600-1500 MHz 20 per cycle+ 2x32 KB 512 KB onboard, no L3 cache 7457 867-1267 MHz 20 per cycle+ 2x32 KB 512 KB onboard, up to 4 MB L3 7457 used in some third-party Mac upgrades, never by Apple 7448 1.0-1.7 GHz 20 per cycle+ 2x32 KB 1024 KB onboard, no L3 cache G5/970 1.6-2.0 GHz 38 per cycle+ 2x32 KB 512 KB onboard 970FX 1.8-2.7 GHz 38 per cycle+ 64+32 KB 512 KB onboard 970MP 1.8-2.5 GHz 38 per cycle+ 64+32 KB 1 MB per core __________ * as used in Apple or Maclone + each AltiVec unit can perform up to 16 simultaneous calculations
- Great CPUs, past and present, John Bayko. See especially sections on 8080/85, Z-80, 6502, 6809, 680×0, 80×86, ARM (used in Newton), PA-RISC, Sparc, Alpha, PowerPC, and Itanium.
- MacTips, RISC, CISC, and Your Mac
- PC Magazine, Motorola and PowerPC (also covers 680×0 series)
- PowerPC 601 v. 603, MacKiDo
- How the G4 Compares to the G3, Scott Barber
- AltiVec, MacKiDo
- G4, MacKiDo
- PowerPC G4 and other news from Microprocessor Forum, Henry Norr, MacInTouch
- Pipelines, MHz, latency, caches, and more, MacKiDo
- AltiVec Performance Comparison, Apple
- MPC7400 PowerPC Microprocessors, Motorola
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