The biggest change in the Apple product line prior to 2006 was the transition from Motorola 680×0 CPUs to the PowerPC (PPC) family of CPUs. Designed by a consortium of Apple, IBM, and Motorola (a.k.a. the AIM Alliance) and based on IBM’s POWER architecture, PowerPC became the most widely used RISC (Reduced Instruction Set Computing) processor with the introduction of the Power Mac line in March 1993.
The great advantage of a RISC processor is that it handles a very simple set of instructions, all the same size, and processes them very quickly.
The first PowerPC chip was the 601, manufactured by IBM (even the ones with the Motorola logo) and initially available in speeds ranging from 50 MHz to 80 MHz using 0.6 micron CMOS technology. The 64-bit CPU was used in the Power Mac 6100, 7100, 7200, and 8100, as well as in most of the first generation of licensed Macintosh clones.
The 601 contains 2.8 million transistors, has a 32 KB unified level 1 (L1) cache, supports an external L2 cache, and can process up to 3 instructions per cycle. Its large L1 cache helped it outperform Intel’s Pentium.
The 601 contains three execution units: one for integers, one for branch processing, and one for floating point.
The 601 was specifically designed to power the IBM RS/6000, so there are many instructions present for that computer that were not included in future PPC designs. This is the only PPC with a unified instruction and data cache; future models contained separate instruction and data caches.
An updated version, known as the 601v or 601+ was also built by IBM; it was available at speeds from 90 MHz to 120 MHz, running at 2x or 3x bus speed.
PowerPC Family Overview
CPU speed* instructions L1 cache L2 cache 601 60-120 MHz 3 per cycle 32 KB external to 1 MB 603 75-160 MHz 2 per cycle 2x8 KB 603e 100-300 MHz 2 per cycle 2x16 KB 604 100-180 MHz 4 per cycle 2x16 KB external to 1 MB 604e 166-233 MHz 6 per cycle 2x32 KB external to 1 MB 604ev 250-350 MHz 6 per cycle 2x32 KB external to 1 MB G3/750 200-450 MHz 3 per cycle 2x32 KB external to 1 MB 750CX 366-466 MHz 3 per cycle 2x32 KB 256 MB onboard 750CXe 400-700 MHz 3 per cycle 2x32 KB 256 MB onboard 750FX 600-900 MHz 3 per cycle 2x32 KB 512 MB onboard 750GX 733-1100 MHz 3 per cycle 2x32 KB 1024 MB onboard G4/7400 350-600 MHz 19 per cycle+ 2x32 KB supports 2 MB L2 cache 7410 466-533 MHz 20 per cycle+ 2x32 KB supports 1 MB L2 cache 7450 667-733 MHz 20 per cycle+ 2x32 KB 256 KB onboard, up to 2 MB L3 7455 600-1420 MHz 20 per cycle+ 2x32 KB 256 KB onboard, up to 2 MB L3 7447A 600-1500 MHz 20 per cycle+ 2x32 KB 512 KB onboard, no L3 cache 7457 867-1267 MHz 20 per cycle+ 2x32 KB 512 KB onboard, up to 4 MB L3 7457 used in some third-party Mac upgrades, never by Apple 7448 1.0-1.7 GHz 20 per cycle+ 2x32 KB 1024 KB onboard, no L3 cache G5/970 1.6-2.0 GHz 38 per cycle+ 2x32 KB 512 KB onboard 970FX 1.8-2.7 GHz 38 per cycle+ 64+32 KB 512 KB onboard 970MP 1.8-2.5 GHz 38 per cycle+ 64+32 KB 1 MB per core __________ * as used in Apple or Maclone + each AltiVec unit can perform up to 16 simultaneous calculations
- Great CPUs, past and present, John Bayko. See especially sections on 8080/85, Z-80, 6502, 6809, 680×0, 80×86, ARM (used in Newton), PA-RISC, Sparc, Alpha, PowerPC, and Itanium.
- MacTips, RISC, CISC, and Your Mac
- PC Magazine, Motorola and PowerPC (also covers 680×0 series)
- PowerPC 601 v. 603, MacKiDo
- How the G4 Compares to the G3, Scott Barber
- AltiVec, MacKiDo
- G4, MacKiDo
- PowerPC G4 and other news from Microprocessor Forum, Henry Norr, MacInTouch
- Pipelines, MHz, latency, caches, and more, MacKiDo
- AltiVec Performance Comparison, Apple
- MPC7400 PowerPC Microprocessors, Motorola
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